1. Field of the Invention
This invention relates generally to integrated circuits having buffers and, more particularly, to a controlled impedance circuit using metal-oxide semiconductor (MOS) technology.
2. Description of the Related Art
In signal transmission environments, digital signals may be transmitted relatively long distances over a transmission line. A transmission line may be a bus, a printed circuit board trace, or any other type of conductive line capable of transporting a digital signal. Typically, for long distance a transmission line has a characteristic impedance of 50 to 75 ohms.
Substantial variations can occur in the performance of integrated circuits simply because the manufacturing processes that are employed cannot be carried out with the desired precision. Indeed, it is not uncommon to find substantial performance variation between integrated circuits of identical design which are manufactured on a single semiconductor wafer but at different locations on the wafer. This includes variations in signal delay (speed), frequency response, and power consumption.
Designers who intend to use integrated circuits must account for all possible variations in ICs' performance. Consequently, in many circumstances designers develop worst case designs, which are designs that assume all IC parameters, or characteristics, to be at their worst specified levels. Manufacturers typically specify, among other things, the minimum and maximum values of both speed and power characteristics of their ICs. That means, of course, that the manufacturer must assure itself somehow that the integrated circuits do lie within the promised bounds of operational characteristics.
In turn, that means that integrated circuits which lie outside the promised bounds have to be discarded as defective. Being able to narrow the variation in speed and power consumption of manufactured ICs would result in higher yield for the IC manufacturer and more desirable integrated circuits for the designer.
An issue related to speed and power dissipation of elements throughout the integrated circuit is the creation of specific impedances that are presented at input/output terminals of the integrated circuits. When signals exit an IC terminal, flow along a signal path over an appreciable distance and enter another IC terminal, signal reflections can be experienced from impedance discontinuities at any point along the signal path, and specifically from the terminals. Most reflections can cause considerable problems in both digital and analog environments (e.g., misdetection of digital signals). It is well known, however, that when the signal path is viewed as a transmission line with a characteristic impedance, undesirable reflections are eliminated when the transmission line is terminated at the sending and/or receiving ends with impedances having a value equal to the characteristic impedance of the transmission line. In other words, what is needed for effective transmission of very high frequency signals through signal paths of appreciable length are integrated circuits where both input and/or output signal terminals have specified and well controlled impedances.
FIG. 1 presents an idealized view of an output terminal 10 that delivers a digital signal to a transmission line 200. The output drive stage of circuitry 100 that is associated with terminal 10 is idealized with impedances 11 and 13. Impedance 11 has one lead connected to fixed positive potential +V through terminal 21 and the other lead connected to one lead of controllable switch 12. The other lead of switch 12 is connected to terminal 10. Similarly, a resistor 13 is connected to a ground potential 19 through a terminal 22 and to controllable switch 14. Like switch 12, switch 14 has one lead connected to terminal 10.
Switch 14 is controlled by a digital input signal S.sub.in, and switch 12 is controlled by its logic inverse, S'.sub.in, so that one switch is closed while the other is open. When switch 14 is closed and switch 12 is open, current flows from transmission line 200 to the ground potential 19, and the impedance that this current encounters is impedance 13. When switch 14 is open and switch 12 is closed, current flows from the fixed positive potential+V into transmission line 200, and the impedance encountered by this current is impedance 11. Ideally, impedances 11 and 13 are equal to each other and set to correspond to the characteristic impedance of the transmission line; e.g., 50 ohms.
FIG. 2 presents a diagrammatic view of the FIG. 1 arrangement. It includes digital impedance circuits 20 and 30. Digital impedance circuit 20 is responsive to input signal S.sub.in. Input signal S.sub.in is applied through input terminal 26 and the ground potential 19 is applied through ground potential terminal 22. Digital impedance circuit 30 is responsive to signal S'.sub.in which is the inverse of S.sub.in derived via inverter 15. Input signal S'.sub.in is applied through input terminal 36 and the positive potential +V is applied through terminal 21. The outputs 23, 33 of impedance circuits 20 and 30 are interconnected and applied to output terminal 10. To provide for the digital control of the impedance value, impedance circuit 20 is responsive to digital control signal bus 21 and impedance circuit 30 is responsive to digital control signal bus 31. The digital impedance circuits 20, 30 are in the form of digitally adjustable transistor arrays, which may be of the type disclosed in U.S. Pat. Nos. 5,243,229 issued to Gabara et al., the disclosure of which is hereby incorporated by reference.
FIG. 3 is an example of a digital transistor array used as the digital impedance circuit 20 (block 30 is of similar construction). As shown, digital transistor array (DTA) 20 comprises a parallel interconnection of MOS transistors 24 between a fixed potential terminal, here ground potential terminal 22 and the output transmission line 23. In controlling impedance values, this arrangement basically represents a parallel connection of resistive paths. The number of transistors 24 used is a design choice. Each of transistors 24 is controlled (at its gate terminal) with a NOR gate 25. Gates 25 are two input gates. One input of gates 25 is connected to input terminal 26 which receives a digital logic signal. The remaining inputs of gates 25 are combined to form a digital control bus (21) which receives control signals for activating selected gates 25. The basic idea behind the FIG. 3 structure is that a number of transistors 24 are fully turned on by applied control signals on bus 21 and by the logic level of an incoming digital logic signal on line 26 which thereby places one or more selected transistors in a low impedance state during one of the "high" or "low" states of the digital logic signal. By placing one or more of transistors 24 in their low impedance state through the applied control signal, the effective impedance of impedance circuit 20 can be lowered to a desired value. The transistors 24 are all turned off during the other of the "high" and "low" states of the digital signal.
Accordingly, if the dimensions of the transistors are carefully sized, and the manufacturing process, operating temperature and power supply voltage V.sub.DD are properly controlled, the digitally adjusted transistor array is able to produce a proper logic level output signal through an impedance which matches the transmission line's impedance. Unfortunately, CMOS transistors have very non-linear I-V characteristics. Referring now to FIG. 4, it can be seen that CMOS transistors have a very small linear region 35 and a much larger non-linear region 32. The slope of these regions 35, 32 represents the impedance of the transistors 24. The typical linear region 35 spans only a few tenths of a volt. Therefore, when a drain-to-source voltage becomes greater than a few tenths of a volt, the output impedance Z of the circuit increases dramatically regardless of the width of the transistors. In addition, the output impedance Z will also be altered by any variations in the manufacturing process, operating temperature and power supply voltage V.sub.DD.
Accordingly, it is difficult to produce a linear output over a large portion of the drain to source voltage swing, which makes it difficult to accurately provide a linear output impedance.